1. Field of the Invention
The present invention relates to a dynamic slew rate controlling method and a device for reducing the variance in simultaneous switching output (SSO).
2. Description of the Prior Art
As the frequency of data processing becomes higher and higher, the requirement of faster input/output transferring rates for operating systems to catch up with the high speed data processing frequencies is growing higher and higher accordingly. The simultaneous switching output has become critical when it comes to input/output rate of operating systems.
When several data bits are switched simultaneously, the input/output buffer (I/O buffer) in an input/output bus (I/O bus) suffers consequential signal variant noises. In other words, when several data bits switch from their “high” to “low” levels or from their “low” to “high” levels, the inductance effect accompanied by transmitted data signals bounces the levels of the power source and ground, leading to a variety of slew rates of data bits on the part of the I/O buffer. When the bounce on power and ground grows larger, the SSO variance becomes larger, and the effective data range becomes narrower.
Please refer to FIG. 1, a schematic diagram illustrates noises resulted from level bounces of a four-bit input/output buffer when one to four data bits are switched simultaneously. Curve A shows the waveform of variance of the power source/ground level as a data bit is switched; curve B shows the waveform of variance as two data bits are switched simultaneously; curve C shows the waveform of variance as three data bits are switched simultaneously; and curve D shows the waveform for variance from four data bits thereby.
The inductance effect leads to voltage drops in accordance with the equation of V=L*(ΔI/Δt), wherein L refers to the inductance and (ΔI/Δt) refers to the current variance in a given period of time. Even if the inductance remains unchanged but several data bits switch at the same time, the voltage drop still accumulates to a certain level, causing bounces in the levels of the power source and ground. Consequently, various changes of the slew rates of data bits lead to an increase of the variance in SSO after the data bits pass through the I/O buffer.
Please refer to FIG. 2A, it shows an original waveform being inputted to the I/O buffer, and in FIG. 2B, it presents various outputted slew rates while different numbers of data bits switch simultaneously. The variance in SSO is represented as “e” in the figure. Four curves A, B, C, and D display the changes of slew rates caused by voltage drops in FIG. 1 of the least, second to least, second to most, and the most simultaneously switching data bits.
When data bits are switching, slew rates thereof are changing gradually. As the diagram shown in FIG. 2B, curve A represents a rising, a smooth and horizontal, and a falling curve finally; curve B represents a gently rising and gently falling curve; curve C is more gentle curve, and curve D shows a least rising and falling curve.
The slew rate variance “e”, arising from the different numbers of simultaneously switching data bits, affects the determination of valid data such as the data segment “f.” The data segment “f” becomes undistinguishable because of high frequency switching such as the simultaneous switching output of data bits in the situation of the I/O buses of the central processing unit, data transmission of system memories and I/O transmission between computer peripherals.
When more and more data bits with the same data pattern switch, the consequential bounces on voltage level of the power source and ground reduces the outputted slew rates of these data bits.
A lot of methods for reducing the SSO variance have been disclosed in the past couple of years such as U.S. Pat. No. 5,229,657, which provides a method and a device for reducing the simultaneous switching noise in the IC output circuit. Please refer to FIG. 3, a circuit diagram showing an output holding register. The output holding register 30 includes a plurality of flip-flops 301, 302, 303, and 304, signal lines 311, 312, 313, and 314, pads 321, 322, 323, and 324, tri-state controllers 331, 332, 333, and 334.
Every flip-flop is supposed to keep one data bit. These signal lines 311, 312, 313, and 314 receive data bits transmitted by a serial shift register 300. Taking the flip-flop 301 for example, the flip-flop 301 receives the timing pulse from the timing pulse line 305 by the timing pulse input end CK thereof and the data bit from the serial shift register 300 by its input end D and transmits the received data bit to the output end Q thereof. The data bit outputted from the output end Q is further transmitted through the tri-state driver 331 to the pad 321 of the circuit. The control signal line 306 controls the status of the tri-state driver 331.
Except the flip-flop 301 directly receives the timing pulse signal by its timing pulse input end CK, other flip-flops 302, 303, and 304 require additional circuits or logic gates for delaying timing pulse signals in order to take care the simultaneous switching noises of data bits when they reach the pads.
Another method of pre-driver skewing is also proposed to prevent noises accompanied by the simultaneous switching of data bits by taking advantage of the RC-delay to reduce the slew rate of pre-stage drivers.
Another method of low-weight coding is also provided by simultaneously decreasing switching bits so as to reduce the SSO variance.
However, the I/O buffer of the prior art has a fixed driving capability to the pre-driver or post-driver under the routine operating circumstance, and is therefore incapable of reducing the SSO variance when several data bits switch simultaneously.